This invention relates to the design and layout of integrated circuits incorporating decoupling capacitors. More particularly, the invention relates to a method and apparatus for selecting certain dimensions in a decoupling capacitor arrangement to increase the decoupling capacitance available on the integrated circuit chip.
The high switching rates used in a modern integrated circuit may cause the supply voltage to degrade at certain points in the circuit, and this reduced supply voltage may cause circuit failures. Capacitors may be used to reduce supply voltage variations arising from high switching rates in the supplied circuits. These decoupling capacitors are connected between the supply voltage and ground in parallel with the supplied circuit. This parallel capacitance tends to decouple the voltage supply from disturbances induced by activity in the supplied circuit, and allow the voltage supply to remain at the intended level.
In earlier integrated circuits, the decoupling capacitance could be placed off-chip due to the relatively slow cycle times at which the earlier circuits operated. The relatively low frequency response exhibited by these off-chip capacitor structures could still accommodate the relatively slow switching rates of the earlier circuits. In addition, the on-chip circuitry itself provided a large amount of near-by decoupling capacitance. As semiconductor fabrication technologies advance, however, circuit devices such as transistors are packed more and more densely on integrated circuit chips. At the same time, the resulting circuits operate at faster cycle times and have less capacitance. At current cycle times on the order of 1 GHz, off-chip capacitance takes many processor cycles to respond. The slow frequency response of off-chip capacitance makes off-chip capacitor arrangements unsuitable for providing the decoupling capacitance necessary to prevent circuit failures in these faster integrated circuit devices. Further, silicon-on-insulator (xe2x80x9cSOIxe2x80x9d) technology allows for still faster cycle times, while reducing the capacitance of on-chip, non-switching circuitry.
In order to provide sufficient decoupling capacitance at the frequency response necessary in modern higher-frequency circuits, the capacitance must be moved closer to the switching circuitry, onto the integrated circuit chip itself. However, there are a number of problems associated with building capacitor structures on-chip. One problem is the space required for capacitor structures. Only a very limited amount of space is commonly available on-chip for decoupling capacitors. Thus, the on-chip capacitors must be implemented so as to provide as much capacitance per unit area of chip space as possible.
Another problem associated with on-chip capacitor structures relates to errors which may occur in fabrication. A capacitor structure generally requires a first layer of conductive material coupled to the chip supply voltage, a second layer of conductive material coupled to ground, and a thin dielectric layer separating the two layers of conductive material. The capacitance and frequency response of the structure is generally enhanced by keeping the layer of dielectric material as thin as possible between the conductive layers, while keeping the two conductive layers electrically isolated from each other. In semiconductor fabrication, however, electrical shorts may occur across a thin layer of dielectric material such as silicon dioxide, for example. A short across a dielectric layer used in semiconductors is more likely to occur in a capacitor structure in which a thin dielectric layer separates two conductive materials over a relatively large area. Where such a short occurs, the resulting excessive current through the semiconductor material may make the chip unusable.
Switching elements may be incorporated into the chip to electrically isolate capacitor structures which include an electrical short. For example, a transistor structure may be connected in series with a capacitor arrangement. If the capacitor arrangement proves to have a short which results in excessive current, the transistor can be switched to isolate the capacitor from the chip power supply. Thus, the chip including such a capacitor structure fault may be usable in spite of the fabrication fault. These series transistors, however, take up valuable chip area and generally complicate the chip structure.
A further problem associated with on-chip capacitor arrangements involves the layout of such arrangements on the chip. A circuit design may leave many different free areas which may be used for on-chip capacitor structures. As used in this disclosure a xe2x80x9cfreexe2x80x9d area may comprise any area not occupied by the normal circuitry of the chip, including areas left specifically for capacitor structures, wiring limited spaces, and chip xe2x80x9cwhite spacexe2x80x9d between irregular shaped circuit blocks. These free areas may include many different sizes and shapes, and thus a number of prior art capacitor cell designs were required to make use of the various areas for decoupling capacitance. However, maintaining a large number of capacitor cells causes logistical problems and requires a great deal of designer time considering a given chip may require hundreds of thousands of decoupling capacitors.
It is an object of the invention to provide a method for laying out on-chip capacitor structures to increase on-chip decoupling capacitance. The method may be easily automated using a computer system and program to vary a single basic capacitor arrangement design so as to effectively fill each desired free area on a chip and provide the highest possible decoupling capacitance using the given area, while requiring minimal design resources.
The method according to the invention is employed using the capacitor arrangement set out in related application Ser. No. 09/435,872, entitled DECOUPLING CAPACITOR STRUCTURE AND METHOD FOR MAKING AN INTEGRATED CIRCUIT CAPACITOR and application Ser. No. 09/435,863 entitled ON-CHIP DECOUPLING CAPACITOR ARRANGEMENT PROVIDING SHORT CIRCUIT PROTECTION. While certain details of this capacitor arrangement are set out in this disclosure for the purposes of describing the present invention, further details of the structure are set out in the related applications.
The capacitor arrangement includes one or more elongated capacitor structures. Each capacitor structure includes a device body formed from a semiconductor material, with the device body bounded on either lateral side by a lateral semiconductor region. Each capacitor structure further includes a dielectric layer overlaying the device body, and an anode body overlaying the dielectric layer in an area defined by the device body. Where the capacitor arrangement includes multiple capacitor structures, the structures are arranged side-by-side with the device bodies forming a series of fingers interdigitated with lateral regions.
With the lateral regions coupled to ground and the anodes coupled to the chip supply voltage, each individual capacitor structure functions as a capacitor between the supply voltage and ground. The overall capacitance provided by the capacitor arrangement for given materials and dielectric thickness is determined by the total area of the anode bodies in the arrangement. Thus, the overall capacitance of a capacitor arrangement used according to the present invention is increased by increasing the height and width of the individual anode fingers in the arrangement to the extent possible and by adding additional capacitor structures in the side-by-side arrangement.
As set out fully in related application Ser. No. 09/435,863, entitled ON-CHIP DECOUPLING CAPACITOR ARRANGEMENT PROVIDING SHORT CIRCUIT PROTECTION the capacitor arrangement provides a current limiting function in the event of a short between an anode body and a corresponding device body or lateral region. The dimensions of the various elements of the capacitor arrangement can be chosen to ensure that for any possible short location, the resulting current through the structure is below some maximum allowable current level.
The dimension requirements in the capacitor arrangement to provide the desired short circuit protection represent the minimum dimension for the height and maximum dimension the width of each capacitor structure in the arrangement. The maximum dimension for the height of each capacitor structure in the capacitor arrangement is determined by the frequency response desired in each capacitor structure. According to the invention, the same basic capacitor arrangement may be varied within the constraints of minimum and maximum height dimensions and permissible width dimensions to make the most efficient use of free space on an integrated circuit chip for on-chip capacitance. Particular capacitor arrangements according to the invention are designed by xe2x80x9cstretchingxe2x80x9d at least one design parameter within certain constraints for the parameter, preferably under computer program control.
The method includes defining at least one sizing parameter for the capacitor arrangement. Preferred sizing parameters include a height dimension range between a maximum and minimum height dimension for the capacitor arrangement, and permissible width dimensions for the capacitor arrangement. Each permissible width dimension comprises a width of the overall capacitor arrangement which may be constructed from one or more capacitor structures. With the parameter or parameters defined, the method includes applying at least one sizing parameter to select a particular capacitor arrangement for a free space on the integrated circuit chip. The selected capacitor arrangement comprises the largest arrangement which is accommodated within the free space, subject to the sizing parameter or parameters employed. Although free areas may be identified manually, such areas are preferably identified automatically from the chip layout.
In one preferred form of the invention, both capacitor height and width parameters are used in selecting a particular capacitor arrangement for a particular free area. A height parameter may comprise a height dimension range between a maximum height dimension for the capacitor arrangement and a minimum height dimension. A width parameter may comprise a plurality of permissible width dimensions based on a single capacitor structure as described above, or multiple capacitor structures. The permissible widths may vary depending on the height dimension, or may be fixed widths. Applying the height and width parameters to select a particular capacitor arrangement comprises selecting a capacitor height dimension from the height dimension range and selecting a capacitor arrangement width dimension from the permissible width dimensions. According to the invention, the selected height dimension comprises the greatest dimension in the range which is less than or equal to the free area height dimension, and within the minimum/maximum range. The selected width dimension comprises the greatest width dimension which is less than or equal to the free area dimension and still one of the plurality of permissible width dimensions. Thus, the method according to the invention selects the largest capacitor arrangement dimensions for the free area while retaining the same basic capacitor arrangement structure. Further, this selection may be done automatically by a computer program, and may be done very late in the design cycle at a time when the free areas are known exactly.
The capacitor arrangement described above and in the related applications provides a high value of capacitance per unit area of the arrangement with a minimal amount of design resources. Applying the present method to effectively size each capacitor arrangement for the particular free areas in the chip layout amplifies the benefits of the capacitor arrangement by making the most of the available free area. The sizing parameters ensure that the resulting capacitor arrangement provides the highest decoupling capacitance at the desired frequency response, while providing integral short circuit protection.
According to the invention, the method may be performed by a computer system programed with software to perform particularly the steps of identifying each free area in the circuit layout and selecting the capacitor arrangement for each free area subject to the defined parameter or parameters. The sizing parameters may be predefined and then entered as inputs to the system, or may be calculated by suitable means in the system, eliminating the need to individually design a large number of these devices.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.